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publication# 17466 rev: n amendment/ 0 issue date: november 2003 mach 4 cpld family high performance e 2 cmos ? in-system programmable logic features high-performance, e 2 cmos 3.3-v & 5-v cpld families flexible architecture for rapid logic designs excellent first-time-fit tm and re? feature speedlocking tm performance for guaranteed ?ed timing central, input and output switch matrices for 100% routability and 100% pin-out retention high speed 7.5ns t pd commercial and 10ns t pd industrial 111.1mhz f cnt 32 to 256 macrocells; 32 to 384 registers 44 to 256 pins in plcc, pqfp, tqfp and bga packages flexible architecture for a wide range of design styles ? /t registers and latches synchronous or asynchronous mode ? edicated input registers programmable polarity reset/ preset swapping advanced capabilities for easy system integration 3.3-v & 5-v jedec-compliant operations ? t ag (ieee 1149.1) compliant for boundary scan testing 3.3-v & 5-v jtag in-system programming pci compliant (-7/-10/-12 speed grades) safe for mixed supply voltage system designs bus-friendly tm inputs and i/os programmable security bit individual output slew rate control advanced e 2 cmos process provides high-performance, cost-effective solutions supported by ispdesignexpert tm software for rapid logic development supports hdl design methodologies with results optimized for mach 4 flexibility to adapt to user requirements software partnerships that ensure customer success lattice and third-party hardware programming support latticepro tm software for in-system programmability support on pcs and automated test equipment programming support on all major programmers including data i/o, bp microsystems, advin, and system general
2m ach 4 family notes: 1. for information on the m4-96/96 device, please refer to the m4-96/96 data sheet at www.latticesemi.com. 2. ?4-xxx?is for 5-v devices. ?4lv-xxx?is for 3.3-v devices. t able 1. mach 4 device features 1, 2 feature m4-32/32 m4lv-32/32 m4-64/32 m4lv-64/32 m4-96/48 m4lv-96/48 m4-128/64 m4lv-128/64 m4-128n/64 m4lv-128n/64 m4-192/96 m4lv-192/96 m4-256/128 m4lv-256/128 macrocells 32 64 96 128 128 192 256 maximum user i/o pins 32 32 48 64 64 96 128 t pd (ns) 7.5 7.5 7.5 7.5 7.5 7.5 7.5 f cnt (mhz) 111 111 111 111 111 111 111 t cos (ns) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 t ss (ns) 5.5 5.5 5.5 5.5 5.5 5.5 5.5 static power (ma) 25 25 50 70 70 85 100 jtag compliant yes yes yes yes no yes yes pci compliant yes yes yes yes yes yes yes
mach 4 family 3 general description the mach 4 family from lattice offers an exceptionally ?xible architecture and delivers a superior complex programmable logic device (cpld) solution of easy-to-use silicon products and software tools. the overall bene?s for users are a guaranteed and predictable cpld solution, faster time-to-market, greater ?xibility and lower cost. the mach 4 devices offer densities ranging from 32 to 256 macrocells with 100% utilization and 100% pin-out retention. the mach 4 family offer 5-v (m4-xxx) and 3.3-v (m4lv-xxx) operation. mach 4 products are 5-v or 3.3-v in-system programmable through the jtag (ieee std. 1149.1) interface. jtag boundary scan testing also allows product testability on automated test equipment for device connectivity. all mach 4 family members deliver first-time-fit and easy system integration with pin-out retention after any design change and re?. for both 3.3-v and 5-v operation, mach 4 products can deliver guaranteed ?ed timing as fast as 7.5 ns t pd and 111 mhz f cnt through the speedlocking feature when using up to 20 product terms per output (table 2). note: 1. c = commercial, i = industrial the mach 4 family offers numerous density-i/o combinations in thin quad flat pack (tqfp), plastic quad flat pack (pqfp), plastic leaded chip carrier (plcc), and ball grid array (bga) packages ranging from 44 to 256 pins (table 3). it also offers i/o safety features for mixed- voltage designs so that the 3.3-v devices can accept 5-v inputs, and 5-v devices do not overdrive 3.3-v inputs. additional features include bus-friendly inputs and i/os, a programmable power- down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition. t able 2. mach 4 speed grades device speed grade 1 -7 -10 -12 -14 -15 -18 m4-32/32 m4lv-32/32 c c, i c, i i c i m4-64/32 m4lv-64/32 c c, i c, i i c i m4-96/48 m4lv-96/48 c c, i c, i i c i m4-128/64 m4lv-128/64 c c, i c, i i c i m4-128n/64 m4lv-128n/64 c c, i c, i i c i m4-192/96 m4lv-192/96 c c, i c, i i c i m4-256/128 m4lv-256/128 c c, i c, i i c i
4m ach 4 family t able 3. mach 4 package and i/o options (number of i/os and dedicated inputs in table) package m4-32/32 m4lv-32/32 m4-64/32 m4lv-64/32 m4-96/48 m4lv-96/48 m4-128/64 m4lv-128/64 m4-128n/64 m4lv-128n/64 m4-192/96 m4lv-192/96 m4lv-256/128 44-pin plcc 32+2 32+2 44-pin tqfp 32+2 32+2 48-pin tqfp 32+2 32+2 84-pin plcc 64+6 100-pin tqfp 48+8 64+6 100-pin pqfp 64+6 144-pin tqfp 96+16 208-pin pqfp 128+14 256-ball bga 128+14
mach 4 family 5 functional description the fundamental architecture of mach 4 devices (figure 1) consists of multiple, optimized pal blocks interconnected by a central switch matrix. the central switch matrix allows communication between pal blocks and routes inputs to the pal blocks. together, the pal blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. the key to being able to make effective use of these devices lies in the interconnect schemes. in mach 4 architecture, the macrocells are ?xibly coupled to the product terms through the logic allocator, and the i/o pins are ?xibly coupled to the macrocells due to the output switch matrix. in addition, more input routing options are provided by the input switch matrix. these resources provide the ?xibility needed to ? designs ef?iently. notes: 1. 16 for mach 4 devices with 1:1 macrocell-i/o cell ratio (see next page). 2. block clocks do not go to i/o cells in m4(lv)-32/32. 3. m4(lv)-192/96 and m4(lv)-256/128 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix. i/o pins clock/input pins central switch matrix i/o pins i/o pins dedicated input pins pal block pal block logic allocator with xor output/ buried macrocells 33/ 34/ 36 16 16 clock generator logic array output switch matrix input switch matrix i/o cells 16 16 8 note 1 note 2 note 3 4 pal block 17466g-001 figure 1. mach 4 block diagram and pal block structure
6m ach 4 family t able 4. architectural summary of mach 4 devices the macrocell-i/o cell ratio is de?ed as the number of macrocells versus the number of i/o cells internally in a pal block (table 4). the central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the pal blocks. feedback signals that return to the same pal block still must go through the central switch matrix. this mechanism ensures that pal blocks in mach 4 devices communicate with each other with consistent, predictable delays. the central switch matrix makes a mach 4 device more advanced than simply several pal devices on a single chip. it allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into pal blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. each pal block consists of: product-term array logic allocator macrocells output switch matrix i/o cells input switch matrix clock generator mach 4 devices m4-64/32, m4lv-64/32 m4-96/48, m4lv-96/48 m4-128/64, m4lv-128/64 m4-128n/64, m4lv-128n/64 m4-192/96, m4lv-192/96 m4-256/128, m4lv-256/128 m4-32/32 m4lv-32/32 macrocell-i/o cell ratio 2:1 1:1 input switch matrix yes yes input registers yes no central switch matrix yes yes output switch matrix yes yes
mach 4 family 7 product-term array the product-term array consists of a number of product terms that form the basis of the logic being implemented. the inputs to the and gates come from the central switch matrix (table 5), and are provided in both true and complement forms for ef?ient logic implementation. logic allocator w ithin the logic allocator, product terms are allocated to macrocells in ?roduct term clusters.? the availability and distribution of product term clusters are automatically considered by the software as it ?s functions within a pal block. the size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. yet when few product terms are used, there will be a minimal number of unused?r wasted?roduct terms left over. the product term clusters available to each macrocell within a pal block are shown in tables 6 and 7. each product term cluster is associated with a macrocell. the size of a cluster depends on the con?uration of the associated macrocell. when the macrocell is used in synchronous mode (figure 2a), the basic cluster has 4 product terms. when the associated macrocell is used in asynchronous mode (figure 2b), the cluster has 2 product terms. note that if the product term cluster is routed to a different macrocell, the allocator con?uration is not determined by the mode of the macrocell actually being driven. the con?uration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. in addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-or gate in the signal path. if included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. a similar asynchronous function can have up to 18 product terms. when the extra product term is used to extend the cluster, the value of the second xor input can be programmed as a 0 or a 1, giving polarity control. the possible con?urations of the logic allocator are shown in figures 3 and 4. t able 5. pal block inputs device number of inputs to pal block m4-32/32 and m4lv-32/32 m4-64/32 and m4lv-64/32 m4-96/48 and m4lv-96/48 m4-128/64 and m4lv-128/64 m4-128n/64 and m4lv-128n/64 33 33 33 33 33 m4-192/96 and m4lv-192/96 m4-256/128 and m4lv-256/128 34 34
8m ach 4 family t able 6. logic allocator for all mach 4 devices (except m4(lv)-32/32) output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 , c 2 m 8 c 7 , c 8 , c 9 , c 10 m 1 c 0 , c 1 , c 2 , c 3 m 9 c 8 , c 9 , c 10 , c 11 m 2 c 1 , c 2 , c 3 , c 4 m 10 c 9 , c 10 , c 11 , c 12 m 3 c 2 , c 3 , c 4 , c 5 m 11 c 10 , c 11 , c 12 , c 13 m 4 c 3 , c 4 , c 5 , c 6 m 12 c 11 , c 12 , c 13 , c 14 m 5 c 4 , c 5 , c 6 , c 7 m 13 c 12 , c 13 , c 14 , c 15 m 6 c 5 , c 6 , c 7 , c 8 m 14 c 13 , c 14 , c 15 m 7 c 6 , c 7 , c 8 , c 9 m 15 c 14 , c 15 t able 7. logic allocator for m4(lv)-32/32 output macrocell available clusters output macrocell available clusters m 0 c 0 , c 1 , c 2 m 8 c 8 , c 9 , c 10 m 1 c 0 , c 1 , c 2 , c 3 m 9 c 8 , c 9 , c 10 , c 11 m 2 c 1 , c 2 , c 3 , c 4 m 10 c 9 , c 10 , c 11 , c 12 m 3 c 2 , c 3 , c 4 , c 5 m 11 c 10 , c 11 , c 12 , c 13 m 4 c 3 , c 4 , c 5 , c 6 m 12 c 11 , c 12 , c 13 , c 14 m 5 c 4 , c 5 , c 6 , c 7 m 13 c 12 , c 13 , c 14 , c 15 m 6 c 5 , c 6 , c 7 m 14 c 13 , c 14 , c 15 m 7 c 6 , c 7 m 15 c 14 , c 15 0 default 0 default prog. polarity to n-1 to n-2 from n-1 to n+1 from n+1 from n+2 basic product term cluster extra product term logic allocator n n to macrocell n 0 default 0 default prog. polarity to n-1 to n-2 from n-1 to n+1 from n+1 from n+2 basic product term cluster extra product term logic allocator nn to macrocell n 17466g-006 figure 2. logic allocator: con?uration of cluster ??set by mode of macrocell ? 17466g-005 a. synchronous mode b. asynchronous mode
mach 4 family 9 note that the con?uration of the logic allocator has absolutely no impact on the speed of the signal. all con?urations have the same delay. this means that designers do not have to decide between optimizing resources or speed; both can be optimized. if not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide xor logic for such functions as data comparison, or it can work with the d-,t-type ?p- ?p to provide for j-k, and s-r register operation. in addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. in this case, the ?st xor input will be a logic 0. this circuit has the ?xibility to route product terms elsewhere without giving up the use of the macrocell. product term clusters do not ?rap?around a pal block. this means that the macrocells at the ends of the block have fewer product terms available. 0 17466g-007 figure 3. logic allocator con?urations: synchronous mode a. basic cluster with xor b. extended cluster, active high c. extended cluster, active low d. basic cluster routed away; single-product-term, active high e. extended cluster routed away 0 17466g-008 figure 4. logic allocator con?urations: asynchronous mode b. extended cluster, active high c. extended cluster, active low e. extended cluster routed away d. basic cluster routed away; single-product-term, active high a. basic cluster with xor
10 mach 4 family macrocell the macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. the macrocell has two fundamental modes: synchronous and asynchronous (figure 5). the mode chosen only affects clocking and initialization in the macrocell. in either mode, a combinatorial path can be used. for combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator. swap d/t/l q ap ar power-up reset pal-block initialization product terms from logic allocator block clk0 block clk1 block clk2 block clk3 to output and input switch matrices common pal-block resource individual macrocell resources from pal-clock generator d/t/l q ap ar power-up reset individual initialization product term from logic allocator block clk0 block clk1 to output and input switch matrices individual clock product term from pal-block clock generator 17466g-010 figure 5. macrocell 17466g-009 a. synchronous mode b. asynchronous mode
mach 4 family 11 the ?p-?p can be con?ured as a d-type or t-type latch. j-k or s-r registers can be synthesized. the primary ?p-?p con?urations are shown in figure 6, although others are possible. flip-?p functionality is de?ed in table 8. note that a j-k latch is inadvisable as it will cause oscillation if both j and k inputs are high. dq ap ar dq ap ar lq ap ar lq ap ar g g tq ap ar 17466g-011 figure 6. primary macrocell con?urations g. combinatorial with programmable polarity a. d-type with xor b. d-type with programmable d polarity c. latch with xor d. latch with programmable d polarity e. t-type with programmable t polarity f. combinatorial with xor
12 mach 4 family note: 1. polarity of clk/le can be programmed although the macrocell shows only one input to the register, the xor gate in the logic allocator allows the d-, t-type register to emulate j-k, and s-r behavior. in this case, the available product terms are divided between j and k (or s and r). when con?ured as j-k, s-r, or t-type, the extra product term must be used on the xor gate input for ?p-?p emulation. in any register type, the polarity of the inputs can be programmed. the clock input to the ?p-?p can select any of the four pal block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. the initialization circuit depends on the mode. in synchronous mode (figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire pal block. t able 8. register/latch operation con?uration input(s) clk/le 1 q+ d-type register d=x d=0 d=1 0,1, ( ) ( ) ( ) q 0 1 t -type register t=x t=0 t=1 0, 1, ( ) ( ) ( ) q q q d-type latch d=x d=0 d=1 1 (0) 0 (1) 0 (1) q 0 1 power-up reset ap d/t/l ar q p al-block initialization product terms a. power-up reset power-up preset ap d/l p al-block initialization product terms ar q 17466g-012 17466g-013 figure 7. synchronous mode initialization con?urations b. power-up preset
mach 4 family 13 a reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing ?xibility. in asynchronous mode (figure 8), a single individual product term is provided for initialization. it can be selected to control reset or preset. note that the reset/preset swapping selection feature effects power-up reset as well. the initialization functionality of the ?p-?ps is illustrated in table 9. the macrocell sends its data to the output switch matrix and the input switch matrix. the output switch matrix can route this data to an output if so desired. the input switch matrix can send the signal back to the central switch matrix as feedback. note: 1. transparent latch is unaffected by ar, ap t able 9. asynchronous reset/preset operation ar ap clk/le 1 q+ 00x see table 8 01x1 10x0 11x0 power-up reset ap d/l/t ar q individual reset product term a. reset power-up preset ap d/l/t ar q individual preset product term b. preset 17466g-014 17466g-015 figure 8. asynchronous mode initialization con?urations
14 mach 4 family output switch matrix the output switch matrix allows macrocells to be connected to any of several i/o cells within a pa l block. this provides high ?xibility in determining pinout and allows design changes to occur without effecting pinout. in mach 4 devices with 2:1 macrocell-i/o cell ratio, each pal block has twice as many macrocells as i/o cells. the mach 4 output switch matrix allows for half of the macrocells to drive i/o cells within a pal block, in combinations according to figure 9. each i/o cell can choose from eight macrocells; each macrocell has a choice of four i/o cells. the mach 4 devices with 1:1 macrocell-i/o cell ratio allow each macrocell to drive one of eight i/o cells (figure 9). m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 each macrocell can drive one of 4 i/o cells in mach 4 devices with 2:1 macrocell-i/o cell ratio. each i/o cell can choose one of 8 macrocells in all mach 4 devices. macrocells mux i/o cell m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 each macrocell can drive one of 8 i/o cells in m4(lv)-32/32 devices. figure 9. mach 4 output switch matrix
mach 4 family 15 t able 10. output switch matrix combinations for mach 4 devices with 2:1 macrocell-i/o cell ratio macrocell routable to i/o cells m0, m1 i/o0, i/o5, i/o6, i/o7 m2, m3 i/o0, i/o1, i/o6, i/o7 m4, m5 i/o0, i/o1, i/o2, i/o7 m6, m7 i/o0, i/o1, i/o2, i/o3 m8, m9 i/o1, i/o2, i/o3, i/o4 m10, m11 i/o2, i/o3, i/o4, i/o5 m12, m13 i/o3, i/o4, i/o5, i/o6 m14, m15 i/o4, i/o5, i/o6, i/o7 i/o cell available macrocells i/o0 m0, m1, m2, m3, m4, m5, m6, m7 i/o1 m2, m3, m4, m5, m6, m7, m8, m9 i/o2 m4, m5, m6, m7, m8, m9, m10, m11 i/o3 m6, m7, m8, m9, m10, m11, m12, m13 i/o4 m8, m9, m10, m11, m12, m13, m14, m15 i/o5 m0, m1, m10, m11, m12, m13, m14, m15 i/o6 m0, m1, m2, m3, m12, m13, m14, m15 i/o7 m0, m1, m2, m3, m4, m5, m14, m15 t able 11. output switch matrix combinations for m4(lv)-32/32 macrocell routable to i/o cells m0, m1, m2, m3, m4, m5, m6, m7 i/o0, i/o1, i/o2, i/o3, i/o4, i/o5, i/o6, i/o7 m8, m9, m10, m11, m12, m13, m14, m15 i/o8, i/o9, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 i/o cell available macrocells i/o0, i/o1, i/o2, i/o3, i/o4, i/o5, i/o6, i/o7 m0, m1, m2, m3, m4, m5, m6, m7 i/o8, i/o9, i/o10, i/o11, i/o12, i/o13, i/o14, i/o15 m8, m9, m10, m11, m12, m13, m14, m15
16 mach 4 family i/o cell the i/o cell (figures 10 and 11) simply consists of a programmable output enable, a feedback path, and ?p-?p (except mach 4 devices with 1:1 macrocell-i/o cell ratio.) an individual output enable product term is provided for each i/o cell. the feedback signal drives the input switch matrix. the i/o cell (figure 10) contains a ?p-?p, which provides the capability for storing the input in a d-type register or latch. the clock can be any of the pal block clocks. both the direct and registered versions of the input are sent to the input switch matrix. this allows for such functions as ?ime-domain-multiplexed?data comparison, where the ?st data value is stored, and then the second data value is put on the i/o pin and compared with the previous stored value. note that the ?p-?p used in the mach 4 i/o cell is independent of the ?p-?ps in the macrocells. it powers up to a logic low. zero-hold-time input register the mach 4 devices have a zero-hold-time (zht) fuse which controls the time delay associated with loading data into all i/o cell registers and latches. when programmed, the zht fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. when the fuse is erased, the setup time to the input storage element is minimized. this feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. input switch matrix the input switch matrix (figures 12 and 13) optimizes routing of inputs to the central switch matrix. without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. the input switch matrix provides additional ways for these signals to enter the central switch matrix. d/l q block clk3 block clk2 block clk1 block clk0 to input switch matrix individual output enable product term from output switch matrix 17466g-017 17466g-018 figure 10. i/o cell for mach 4 devices with 2:1 macrocell-i/o cell ratio figure 11. i/o cell for mach 4 devices with 1:1 macrocell-i/o cell ratio to input switch matrix individual output enable product term from output switch matrix power-up reset
mach 4 family 17 p al block clock generation each mach 4 device has four clock pins that can also be used as inputs. these pins drive a clock generator in each pal block (figure 14). the clock generator provides four clock signals that can be used anywhere in the pal block. these four pal block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. t able 12 lists the possible combinations. note: 1. m4(lv)-32/32 and m4(lv)-64/32 have only two clock pins, gclk0 and gclk1. gclk2 is tied to gclk0, and gclk3 is tied to gclk1. to central switch matrix from macrocell 2 from input cell direct from macrocell 1 registered/latched 17466g-002 17466g-003 figure 12. mach 4 with 2:1 macrocell-i/o cell ratio - input switch matrix figure 13. mach 4 with 1:1 macrocell-i/o cell ratio - input switch matrix to central switch matrix from macrocell from i/o pin gclk0 gclk1 gclk2 gclk3 block clk0 (gclk0 or gclk1) block clk1 (gclk1 or gclk0) block clk2 (gclk2 or gclk3) block clk3 (gclk3 or gclk2) 17466g-004 figure 14. pal block clock generator 1
18 mach 4 family note: 1. values in parentheses are for the m4(lv)-32/32 and m4(lv)-64/32. this feature provides high ?xibility for partitioning state machines and dual-phase clocks. it also allows latches to be driven with either polarity of latch enable, and in a master-slave con?uration. t able 12. pal block clock combinations 1 block clk0 block clk1 block clk2 block clk3 gclk0 gclk1 gclk0 gclk1 x x x x gclk1 gclk1 gclk0 gclk0 x x x x x x x x gclk2 (gclk0) gclk3 (gclk1 ) gclk2 (gclk0) gclk3 (gclk1 ) x x x x gclk3 (gclk1) gclk3 (gclk1) gclk2 (gclk0 ) gclk2 (gclk0 )
mach 4 family 19 mach 4 timing model the primary focus of the mach 4 timing model is to accurately represent the timing in a mach 4 device, and at the same time, be easy to understand. this model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. a signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. the input register speci?ations are also reported as internal feedback. when a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. the parameter, t buf , is de?ed as the time it takes to go from feedback through the output buffer to the i/o pad. if a signal goes to the internal feedback rather than to the i/o pad, the parameter designator is followed by an ?? by adding t buf to this internal parameter, the external parameter is derived. for example, t pd = t pdi + t buf . a diagram representing the modularized mach 4 timing model is shown in figure 15. refer to the technical note entitled mach 4 timing and high speed design for a more detailed discussion about the timing parameters. speedlocking for guaranteed fixed timing the mach 4 architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an xor gate without incurring additional timing delays. the design of the switch matrix and pal blocks guarantee a ?ed pin-to-pin delay that is independent of the logic required by the design. other competitive cplds incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. speed and speedlocking combine to give designs easy access to the performance required in today? designs. (external feedback) (internal feedback) input reg/ input latch t sirs t hirs t sil t hil t sirz t hirz t silz t hilz t pdili t icosi t igosi t pdilzi q t ss(t) t sa(t) t h(s/a) t s(s/a)l t h(s/a)l t srr t pdi t pdli t co(s/a)i t go(s/a)i t sri comb/dff/tff/ latch/sr*/jk* s/r in blk clk out t pl t buf t ea t er t slw q central switch matrix *emulated 17466g-025 figure 15. mach 4 timing model
20 mach 4 family ieee 1149.1-compliant boundary scan testability all mach 4 devices, except the m4(lv)-128n/64, have boundary scan cells and are compliant to the ieee 1149.1 standard. this allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for veri?ation. in addition, these devices can be linked into a board-level serial scan path for more complete board-level testing. ieee 1149.1-compliant in-system programming programming devices in-system provides a number of signi?ant bene?s including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-?ld modi?ations. all mach 4 devices provide in-system programming (isp) capability through their boundary scantest access ports. this capability has been implemented in a manner that ensures that the port remains compliant to the ieee 1149.1 standard. by using ieee 1149.1 as the communication interface through which isp is achieved, customers get the bene? of a standard, well-de?ed interface. mach 4 devices can be programmed across the commercial temperature and voltage range. the pc-based latticepro software facilitates in-system programming of mach 4 devices. latticepro takes the jedec ?e output produced by the design implementation software, along with information about the jtag chain, and creates a set of vectors that are used to drive the jtag chain. latticepro software can use these vectors to drive a jtag chain via the parallel port of a pc. alternatively, latticepro software can output ?es in formats understood by common automated test equipment. this equpment can then be used to program mach 4 devices during the testing of a circuit board. pci compliant mach 4 devices in the -7/-10/-12 speed grades are compliant with the pci local bus speci?ation version 2.1, published by the pci special interest group (sig). the 5-v devices are fully pci-compliant. the 3.3-v devices are mostly compliant but do not meet the pci condition to clamp the inputs as they rise above v cc because of their 5-v input tolerant feature. safe for mixed supply voltage system designs both the 3.3-v and 5-v v cc mach 4 devices are safe for mixed supply voltage system designs. the 5-v devices will not overdrive 3.3-v devices above the output voltage of 3.3 v, while they accept inputs from other 3.3-v devices. the 3.3-v device will accept inputs up to 5.5 v. both the 5-v and 3.3-v versions have the same high-speed performance and provide easy-to-use mixed- voltage design capability. bus-friendly inputs and i/os all mach 4 devices have inputs and i/os which feature the bus-friendly circuitry incorporating two inverters in series which loop back to the input. this double inversion weakly holds the input at its last driven logic state. while it is good design practice to tie unused pins to a known state, the bus-friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. at power-up, the bus-friendly latches are reset to a logic level ?.?for the circuit diagram, please refer to the document entitled mach endurance characteristics on the lattice/vantis data book cd-rom or lattice web site.
mach 4 family 21 power management each individual pal block in mach 4 devices features a programmable low-power mode, which results in power savings of up to 50%. the signal speed paths in the low-power pal block will be slower than those in the non-low-power pal block. this feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. programmable slew rate each mach 4 device i/o has an individually programmable output slew rate control bit. each output can be individually con?ured for the higher speed transition (3 v/ns) or for the lower noise transition (1 v/ns). for high-speed designs with long, unterminated traces, the slow-slew rate will introduce fewer re?ctions, less noise, and keep ground bounce to a minimum. for designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. the slew rate is adjusted independent of power. power-up reset/set all ?p-?ps power up to a known state for predictable system initialization. if a macrocell is con?ured to set on a signal from the control generator, then that macrocell will be set during device power-up. if a macrocell is con?ured to reset on a signal from the control generator or is not con?ured for set/reset, then that macrocell will reset on power-up. to guarantee initialization values, the v cc rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. security bit a programmable security bit is provided on the mach 4 devices as a deterrent to unauthorized copying of the array con?uration patterns. once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. programming and veri?ation are also defeated by the security bit. the bit can only be reset by erasing the entire device.
22 mach 4 family macrocell m0 c0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 b 89 m0 m4(lv)-64/32, m4(lv)-96/48, m4(lv)-128/64 a b 16 17 17 17 m4(lv)-192/96, m4(lv)-256/128 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 o0 o1 o2 o3 o4 o5 o6 o7 m15 clk0 clk1 clk2 clk3 i/o cell i/o0 clock generator macrocell macrocell macrocell macrocell macrocell macrocell central switch matrix macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell 24 a 0 4 16 16 c1 c2 i/o cell i/o1 c3 c4 i/o cell i/o2 c5 c6 i/o cell i/o3 c7 c8 i/o cell i/o4 c9 c10 i/o cell i/o5 c11 c12 i/o cell i/o6 c13 c14 i/o cell input switch matrix i/o7 c15 logic allocator output switch matrix figure 16. pal block for mach 4 with 2:1 macrocell - i/o cell ratio
mach 4 family 23 17466h-042 macrocell m0 c0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 m15 17 97 m0 m1 m2 m3 m4 m5 m6 m7 m8 m9 m10 m11 m12 m13 m14 o0 o2 o4 o6 o8 o10 o12 o14 m15 i/o cell i/o0 clock generator macrocell macrocell macrocell macrocell macrocell macrocell central switch matrix macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell macrocell o1 i/o cell i/o1 32 16 0 2 16 16 c1 c2 i/o cell i/o2 o3 i/o cell i/o3 o5 i/o cell i/o5 o7 i/o cell i/o7 c3 c4 i/o cell i/o4 c5 c6 i/o cell i/o6 c7 c8 i/o cell i/o8 o9 i/o cell i/o9 o11 i/o cell i/o11 c9 c10 i/o cell i/o10 c11 c12 i/o cell i/o12 o13 i/o cell i/o13 o15 i/o cell i/o15 c13 c14 i/o cell input switch matrix i/o14 c15 logic allocator output switch matrix output switch matrix clk0/i0 clk0/i1 figure 17. pal block for m4(lv)-32/32
24 mach 4 family block diagram ?m4(lv)-32/32 17466h-019 central switch matrix 2 2 clk0/i0, clk1/i1 i/o8?/o15 i/o0?/o7 i/o16?/o23 i/o24?/o31 i/o cells output switch matrix macrocells 8 8 16 8 8 8 33 4 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 98 and logic array and logic allocator clock generator input switch matrix 8 8 16 8 8 8 2 8 8 i/o cells output switch matrix macrocells 8 8 16 8 8 8 8 8 i/o cells output switch matrix macrocells 66 x 98 and logic array and logic allocator 8 8 16 8 8 8 2 8 8 input switch matrix input switch matrix input switch matrix clock generator oe oe oe oe block a block b 33
mach 4 family 25 block diagram ?m4(lv)-64/32 17466h-020 central switch matrix 2 2 clk0/i0, clk1/i1 i/o0?/o7 i/o24?/o31 i/o16?/o23 i/o8?/o15 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 2 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 2 8 8 input switch matrix input switch matrix input switch matrix clock generator clock generator oe oe oe oe block a block b block d block c
26 mach 4 family block diagram ?m4(lv)-96/48 4 4 4 clk0/i0, clk1/i1, clk2/i4, clk3/i5 i2, i3, i6, i7 i/o16?/o23 i/o8?/o15 i/o0?/o7 i/o40?/o47 i/o32?/o39 i/o24?/o31 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 oe input switch matrix input switch matrix input switch matrix clock generator clock generator clock generator input switch matrix oe oe oe oe oe block c block b block a block d block e block f central switch matrix 17466g-021
mach 4 family 27 block diagram ?m4(lv)-128n/64 and m4(lv)-128/64 central switch matrix 4 4 2 clk0/i0, clk1/i1, clk2/i3, clk3/i4 i2, i5 i/o0?/o7 i/o8?/o15 i/o16?/o23 i/o24?/031 i/o32?/o39 i/o40?/o47 i/o48?/o55 i/o56?/o63 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator clock generator input switch matrix 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator 16 16 24 16 16 8 33 4 4 4 8 8 i/o cells output switch matrix macrocells 66 x 90 and logic array and logic allocator oe 16 16 24 16 16 8 33 4 4 4 8 8 input switch matrix input switch matrix input switch matrix clock generator clock generator clock generator input switch matrix input switch matrix clock generator oe oe oe oe oe oe oe block a block b block c block d block h block g block f block e 17466h-022
28 mach 4 family block diagram ?m4(lv)-192/96 central switch matrix block b i/o8?/o15 clk0?lk3 i/o32?/o39 block e i/o56?/o63 block h i/o48?/o55 block g i0?15 i/o40?/o47 block f block a i/o0?/o7 block k i/o80?/o87 block l i/o88?/o95 block c i/o16?/o23 block d i/o24?/o31 i/o72?/o79 block j i/o64?/o71 block i i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix 16 4 4 oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 16 8 4 16 24 8 16 16 34 34 34 34 34 34 34 34 34 4 4 oe oe 8 16 8 4 16 24 8 16 16 4 4 8 24 4 8 8 16 16 4 4 16 16 oe 8 24 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 24 16 16 8 16 8 4 16 oe 4 4 24 16 16 8 16 16 4 8 8 oe 4 4 24 16 16 8 16 16 4 8 8 4 4 8 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 4 4 oe 17466g-067
mach 4 family 29 block diagram ?m4(lv)-256/128 central switch matrix block b i/o8?/o15 clk0?lk3 i/o48?/o55 block g i/o72?/o79 block j i/o64?/o71 block i i0?13 i/o56?/o63 block h block a i/o0?/o7 block o i/o112?/o119 block p i/o120?/o127 block c i/o16?/o23 block d i/o24?/o31 block e i/o32?/o39 block f i/o40?/o47 i/o104?/o111 block n i/o96?/o103 block m i/o88?/o95 block l i/o80?/o87 block k i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix i/o cells macrocells 68 x 90 and logic array and logic allocator clock generator input switch matrix output switch matrix 14 4 4 oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 34 24 16 16 8 16 8 4 16 oe 4 4 34 24 16 16 8 16 16 4 8 8 oe 4 4 34 24 16 16 8 16 16 4 8 8 4 4 8 34 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 34 4 4 oe oe 8 16 8 4 16 24 8 16 16 34 4 4 8 24 34 4 8 8 16 16 4 4 16 16 oe 8 24 34 4 8 8 16 16 4 4 16 16 oe oe 4 4 8 34 24 16 16 8 16 8 4 16 oe 4 4 34 24 16 16 8 16 16 4 8 8 oe 4 4 34 24 16 16 8 16 16 4 8 8 4 4 8 34 24 16 16 8 16 8 4 16 oe 8 16 8 4 16 24 8 16 16 34 4 4 oe 17466g-024
mach 4 family 30 absolute maximum ratings m4 storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . . -55 c to +100 c device junction temperature . . . . . . . . . . . . . +130 c supply voltage with respect to ground . . . . . . . . . . . -0.5 v to +7.0 v dc input voltage . . . . . . . . . . . . -0.5 v to v cc + 0.5 v static discharge voltage . . . . . . . . . . . . . . . . . 2000 v latchup current (t a = -40 c to +85 c). . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r eliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . . +4.75 v to +5.25 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . +4.50 v to +5.5 v operating ranges de?e those limits between which the func- tionality of the device is guaranteed. notes: 1. total i ol for one pal block should not exceed 64 ma. 2. these are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 4. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. v out = 0.5 v has been chosen to avoid test problems caused by tester ground degradation. 5-v dc characteristics over operating ranges parameter symbol parameter description test conditions min typ max unit v oh output high voltage i oh = ?.2 ma, v cc = min, v in = v ih or v il 2.4 v i oh = 0 ma, v cc = max, v in = v ih or v il 3.3 v v ol output low voltage i ol = 24 ma, v cc = min, v in = v ih or v il (note 1) 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs (note 2) 2.0 v v il input low voltage guaranteed input logical low voltage for all inputs (note 2) 0.8 v i ih input high leakage current v in = 5.25 v, v cc = max (note 3) 10 a i il input low leakage current v in = 0 v, v cc = max (note 3) ?0 a i ozh off-state output leakage current high v out = 5.25 v, v cc = max, v in = v ih or v il (note 3) 10 a i ozl off-state output leakage current low v out = 0 v, v cc = max , v in = v ih or v il (note 3) ?0 a i sc output short-circuit current v out = 0.5 v, v cc = max (note 4) ?0 ?60 ma
mach 4 family 31 absolute maximum ratings m4lv storage temperature . . . . . . . . . . . . . .-65 c to +150 c ambient temperature with power applied . . . . . . . . . . . . . . -55 c to +100 c device junction temperature . . . . . . . . . . . . . +130 c supply voltage with respect to ground . . . . . . . . . . . -0.5 v to +4.5 v dc input voltage . . . . . . . . . . . . . . . . . -0.5 v to 6.0 v static discharge voltage . . . . . . . . . . . . . . . . . 2000 v latchup current (t a = -40 c to +85 c). . . . . . . 200 ma stresses above those listed under absolute maximum ratings may cause permanent device failure. functionality at or above these limits is not implied. exposure to absolute maximum ratings for extended periods may affect device r eliability. operating ranges commercial (c) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . . 0 c to +70 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +3.0 v to +3.6 v industrial (i) devices ambient temperature (t a ) operating in free air . . . . . . . . . . . . . . -40 c to +85 c supply voltage (v cc ) with respect to ground . . . . . . . . . . . +3.0 v to +3.6 v operating ranges de?e those limits between which the func- tionality of the device is guaranteed. notes: 1. total i ol for one pal block should not exceed 64 ma. 2. i/o pin leakage is the worst case of i il and i ozl (or i ih and i ozh ). 3. not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. 3.3-v dc characteristics over operating ranges parameter symbol parameter description test conditions min typ max unit v oh output high voltage v cc = min v in = v ih or v il i oh = ?00 av cc ?0.2 v i oh = ?.2 ma 2.4 v v ol output low voltage v cc = min v in = v ih or v il (note 1) i ol = 100 a 0.2 v i ol = 24 ma 0.5 v v ih input high voltage guaranteed input logical high voltage for all inputs 2.0 5.5 v v il input low voltage guaranteed input logical low voltage for all inputs ?.3 0.8 v i ih input high leakage current v in = 3.6 v, v cc = max (note 2) 5 a i il input low leakage current v in = 0 v, v cc = max (note 2) ? a i ozh off-state output leakage current high v out = 3.6 v, v cc = max v in = v ih or v il (note 2) 5 a i ozl off-state output leakage current low v out = 0 v, v cc = max v in = v ih or v il (note 2) ? a i sc output short-circuit current v out = 0.5 v, v cc = max (note 3) ?5 ?60 ma
32 mach 4 family mach 4 timing parameters over operating ranges 1 -7 -10 -12 -14 -15 -18 unit min max min max min max min max min max min max combinatorial delay: t pdi internal combinatorial propagation delay 5.5 8.0 10.0 12.0 13.0 16.0 ns t pd combinatorial propagation delay 7.5 10.0 12.0 14.0 15.0 18.0 ns registered delays: t ss synchronous clock setup time, d-type register 5.5 6.0 7.0 10.0 10.0 12.0 ns t sst synchronous clock setup time, t-type register 6.5 7.0 8.0 11.0 11.0 13.0 ns t sa asynchronous clock setup time, d-type register 3.5 4.0 5.0 8.0 8.0 10.0 ns t sat asynchronous clock setup time, t-type register 4.5 5.0 6.0 9.0 9.0 11.0 ns t hs synchronous clock hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t ha asynchronous clock hold time 3.5 4.0 5.0 8.0 8.0 10.0 ns t cosi synchronous clock to internal output 3.5 4.5 6.0 8.0 8.0 10.0 ns t cos synchronous clock to output 5.5 6.5 8.0 10.0 10.0 12.0 ns t coai asynchronous clock to internal output 7.5 10.0 12.0 16.0 16.0 18.0 ns t coa asynchronous clock to output 9.5 12.0 14.0 18.0 18.0 20.0 ns latched delays: t ssl synchronous latch setup time 6.0 7.0 8.0 10.0 10.0 12.0 ns t sal asynchronous latch setup time 4.0 4.0 5.0 8.0 8.0 10.0 ns t hsl synchronous latch hold time 0.0 0.0 0.0 0.0 0.0 0.0 ns t hal asynchronous latch hold time 4.0 4.0 5.0 8.0 8.0 10.0 ns t pdli t ransparent latch to internal output 8.0 10.0 12.0 15.0 15.0 18.0 ns t pdl propagation delay through transparent latch to output 10.0 12.0 14.0 17.0 17.0 20.0 ns t gosi synchronous gate to internal output 4.0 5.5 8.0 9.0 9.0 10.0 ns t gos synchronous gate to output 6.0 7.5 10.0 11.0 11.0 12.0 ns t goai asynchronous gate to internal output 9.0 11.0 14.0 17.0 17.0 20.0 ns t goa asynchronous gate to output 11.0 13.0 16.0 19.0 19.0 22.0 ns input register delays: t sirs input register setup time 2.0 2.0 2.0 2.0 2.0 2.0 ns t hirs input register hold time 3.0 3.0 3.0 4.0 4.0 4.0 ns t icosi input register clock to internal feedback 3.5 4.5 6.0 6.0 6.0 6.0 ns input latch delays: t sil input latch setup time 2.0 2.0 2.0 2.0 2.0 2.0 ns t hil input latch hold time 3.0 3.0 3.0 4.0 4.0 4.0 ns t igosi input latch gate to internal feedback 4.0 4.0 4.0 5.0 5.0 6.0 ns t pdili t ransparent input latch to internal feedback 2.0 2.0 2.0 2.0 2.0 2.0 ns input register delays with zht option: t sirz input register setup time - zht 6.0 6.0 6.0 6.0 6.0 6.0 ns t hirz input register hold time - zht 0.0 0.0 0.0 0.0 0.0 0.0 ns
mach 4 family 33 input latch delays with zht option: t silz input latch setup time - zht 6.0 6.0 6.0 6.0 6.0 6.0 ns t hilz input latch hold time - zht 0.0 0.0 0.0 0.0 0.0 0.0 ns t pdilzi t ransparent input latch to internal feedback - zht 6.0 6.0 6.0 6.0 6.0 6.0 ns output delays: t buf output buffer delay 2.0 2.0 2.0 2.0 2.0 2.0 ns t slw slow slew rate delay adder 2.5 2.5 2.5 2.5 2.5 2.5 ns t ea output enable time 9.5 10.0 12.0 15.0 15.0 17.0 ns t er output disable time 9.5 10.0 12.0 15.0 15.0 17.0 ns power delay: t pl power-down mode delay adder 2.5 2.5 2.5 2.5 2.5 2.5 ns reset and preset delays: t sri asynchronous reset or preset to internal register output 10.0 12.0 14.0 18.0 18.0 20.0 ns t sr asynchronous reset or preset to register output 12.0 14.0 16.0 20.0 20.0 22.0 ns t srr asynchronous reset and preset register recovery time 8.0 8.0 10.0 15.0 15.0 17.0 ns t srw asynchronous reset or preset width 10.0 10.0 12.0 15.0 15.0 17.0 ns clock/le width: t wls global clock width low 3.0 5.0 6.0 6.0 6.0 7.0 ns t whs global clock width high 3.0 5.0 6.0 6.0 6.0 7.0 ns t wla product term clock width low 4.0 5.0 8.0 9.0 9.0 10.0 ns t wha product term clock width high 4.0 5.0 8.0 9.0 9.0 10.0 ns t gws global gate width low (for low transparent) or high (for high transparent) 5.0 5.0 6.0 6.0 6.0 7.0 ns t gwa product term gate width low (for low transparent) or high (for high transparent) 4.0 5.0 6.0 9.0 9.0 11.0 ns t wirl input register clock width low 4.5 5.0 6.0 6.0 6.0 7.0 ns t wirh input register clock width high 4.5 5.0 6.0 6.0 6.0 7.0 ns t wil input latch gate width 5.0 5.0 6.0 6.0 6.0 7.0 ns mach 4 timing parameters over operating ranges 1 (continued) -7 -10 -12 -14 -15 -18 unit min max min max min max min max min max min max
34 mach 4 family notes: 1. see ?ach switching test circuit?document on the literature download page of the lattice web site. 2. this parameter does not apply to ?p-?ps in the emulated mode since the feedback path is required for emulation. capacitance 1 note: 1. these parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modi?d wh ere this parameter may be affected. frequency: f maxs external feedback, d-type, min of 1/(t wls + t whs ) or 1/(t ss + t cos ) 90.9 80.0 66.7 50.0 50.0 41.7 mhz external feedback, t-type, min of 1/(t wls + t whs ) or 1/(t sst + t cos ) 83.3 74.1 62.5 47.6 47.6 40.0 mhz internal feedback (f cnt ), d-type, min of 1/(t wls + t whs ) or 1/(t ss + t cosi ) 111.1 95.2 76.9 55.6 55.6 45.5 mhz internal feedback (f cnt ), t-type, min of 1/(t wls + t whs ) or 1/(t sst + t cosi ) 100.0 87.0 71.4 52.6 52.6 43.5 mhz no feedback 2 , min of 1/(t wls + t whs ), 1/(t ss + t hs ) or 1/(t sst + t hs ) 153.8 100.0 83.3 83.3 83.3 71.4 mhz f maxa external feedback, d-type, min of 1/(t wla + t wha ) or 1/(t sa + t coa ) 76.9 62.5 52.6 38.5 38.5 33.3 mhz external feedback, t-type, min of 1/(t wla + t wha ) or 1/(t sat + t coa ) 71.4 58.8 50.0 37.0 37.0 32.3 mhz internal feedback (f cnta ), d-type, min of 1/(t wla + t wha ) or 1/(t sa + t coai ) 90.9 71.4 58.8 41.7 41.7 35.7 mhz internal feedback (f cnta ), t-type, min of 1/(t wla + t wha ) or 1/(t sat + t coai ) 83.3 66.7 55.6 40.0 40.0 34.5 mhz no feedback 2 , min of 1/(t wla + t wha ), 1/(t sa + t ha ) or 1/(t sat + t ha ) 125.0 100.0 62.5 55.6 55.6 50.0 mhz f maxi maximum input register frequency, min of 1/(t wirh + t wirl ) or 1/(t sirs + t hirs ) 111.0 100.0 83.3 83.3 83.3 71.4 mhz parameter symbol parameter description test conditions typ unit c in input capacitance v in =2.0 v 3.3 v or 5 v, 25?, 1 mhz 6 pf c i/o output capacitance v out =2.0v 3.3 v or 5 v, 25?, 1 mhz 8 pf mach 4 timing parameters over operating ranges 1 (continued) -7 -10 -12 -14 -15 -18 unit min max min max min max min max min max min max
mach 4 family 35 i cc vs. frequency these curves represent the typical power consumption for a particular device at system frequen- cy. the selected ?ypical?pattern is a 16-bit up-down counter. this pattern ?ls the device and exercises every macrocell. maximum frequency shown uses internal feedback and a d-type reg- ister. power/speed are optimized to obtain the highest counter frequency and the lowest power. the highest frequency (lsbs) is placed in common pal blocks, which are set to high power. the lowest frequency signals (msbs) are placed in a common pal block and set to lowest power. 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 110 120 130 v cc = 5 v or 3.3 v, t a = 25?c i cc (ma) frequency (mhz) 17466g-066 m4(lv)-32/32 m4(lv)-64/32 m4(lv)-96/48 m4(lv)-128/64 m4(lv)-192/96 m4(lv)-256/128 figure 18. mach 4 i cc curves at high speed mode 350 300 250 200 150 100 50 0 0 10 20 30 40 50 60 70 80 90 100 110 120 v cc = 5 v or 3.3 v, t a = 25?c m4(lv)-32/32 i cc (ma) frequency (mhz) 17466g-065 m4(lv)-64/32 m4(lv)-96/48 m4(lv)-128/64 m4(lv)-192/96 m4(lv)-256/128 figure 19. mach 4 i cc curves at low power mode
36 mach 4 family 44-pin plcc connection diagram (m4(lv)-32/32 and m4(lv)-64/32) t op view 44-pin plcc pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out 1 44 43 42 5 4 3 2 641 40 7 8 9 10 11 12 13 14 15 16 17 23 24 25 26 19 20 21 22 18 27 28 39 38 37 36 35 34 33 32 31 30 29 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 a2 a1 a0 a8 a9 a10 a11 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 i/o12 i/o13 i/o14 i/o15 vcc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 m4(lv)-32/32 m4(lv)-32/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 17466g-026 i/o cell (0-7) p al block (a-d) c7
mach 4 family 37 44-pin tqfp connection diagram (m4(lv)-32/32 and m4(lv)-64/32) t op view 44-pin tqfp pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out i/o12 i/o13 i/o14 i/o15 vcc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 i/o27 i/o26 i/o25 i/o24 tdo gnd clk1/i1 tms i/o23 i/o22 i/o21 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 i/o5 i/o6 i/o7 tdi clk0/i0 gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 a2 a1 a0 a8 a9 a10 a11 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 m4(lv)-32/32 m4(lv)-32/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 i/o cell (0-7) p al block (a-d) c7
38 mach 4 family 48-pin tqfp connection diagram (m4(lv)-32/32 and m4(lv)-64/32) t op view 48-pin tqfp pin designations clk/i = clock or input gnd = ground i/o = input/output v cc = supply voltage nc = no connect tdi = test data in tck = test clock tms = test mode select tdo = test data out i/o12 i/o13 i/o14 i/o15 vcc nc gnd i/o16 i/o17 i/o18 i/o19 i/o20 b4 b5 b6 b7 c7 c6 c5 c4 c3 a12 a13 a14 a15 b15 b14 b13 b12 b11 i/o4 i/o3 i/o2 i/o1 i/o0 gnd nc vcc i/o31 i/o30 i/o29 i/o28 a3 a4 a5 a6 a7 d7 d6 d5 d4 a3 a4 a5 a6 a7 b7 b6 b5 b4 i/o27 i/o26 i/o25 i/o24 tdo gnd nc clk1/i1 tms i/o23 i/o22 i/o21 d3 d2 d1 d0 c0 c1 c2 b3 b2 b1 b0 b8 b9 b10 i/o5 i/o6 i/o7 tdi clk0/i0 nc gnd tck i/o8 i/o9 i/o10 i/o11 a2 a1 a0 b0 b1 b2 b3 a2 a1 a0 a8 a9 a10 a11 1 2 3 4 5 6 7 8 9 10 11 12 33 34 35 36 32 31 30 29 28 27 26 25 44 45 46 47 48 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 m4(lv)-32/32 m4(lv)-32/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 m4(lv)-64/32 17466g-028 i/o cell (0-7) p al block (a-d) c7
mach 4 family 39 100-pin tqfp connection diagram (m4(lv)-96/48) t op view 100-pin tqfp pin designations clk/i = clock or input gnd = ground i= input i/o = input/output v cc = supply voltage nc = no connect tdi = test data in tck = test clock tms = test mode select tdo = test data out 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 nc tdi nc nc i/o6 i/o7 i/o8 i/o9 i/o10 i/o11 i0/clk0 v cc gnd i1/clk1 i/o12 i/o13 i/o14 i/o15 i/o16 i/o17 nc nc tms tck nc a1 a0 b0 b1 b2 b3 b4 b5 b6 b7 c0 c1 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd nc nc i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 nc i2 nc nc gnd v cc i3 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 nc nc gnd c2 c3 c4 c5 c6 c7 d7 d6 d5 d4 d3 d2 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd nc nc i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 i7 v cc gnd nc nc i6 nc i/o47 i/o46 i/o45 i/o44 i/o43 i/o42 nc nc gnd a2 a3 a4 a5 a6 a7 f7 f6 f5 f4 f3 f2 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 nc tdo nc nc nc i/o41 i/o40 i/o39 i/o38 i/o37 i/o36 i5/clk3 gnd v cc i4/clk2 i/o35 i/o34 i/o33 i/o32 i/o31 i/o30 nc nc nc nc f1 f0 e0 e1 e2 e3 e4 e5 e6 e7 d0 d1 17466g-029 i/o cell (0-7) p al block (a-f) c7
40 mach 4 family 84-pin plcc connection diagram (m4(lv)-128n/64) t op view 84-pin plcc note: pin-compatible with the mach131, mach231, mach435. pin designations clk/i = clock or input gnd = ground i= input i/o = input/output v cc = supply voltage 1 2 3 81 82 83 84 6 7 8 9 4 5 80 76 77 78 79 75 12 13 14 15 16 17 18 19 20 21 23 24 25 26 27 28 29 30 31 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 43 42 41 40 47 46 45 44 37 36 35 34 39 38 33 48 52 51 50 49 10 22 11 32 53 74 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 clk 0 /i 0 v cc gnd clk 1 /i 1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 gnd i/o8 gnd i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 clk 3 /i 4 v cc clk 2 /i 3 i/o47 g7 g6 g5 g4 g3 g2 g1 g0 f0 f1 f2 f3 f4 f5 f6 f7 b7 b6 b5 b4 b3 b2 b1 b0 c0 c1 c2 c3 c4 c5 c6 c7 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 gnd i/o40 gnd v cc i/o0 i/o62 i/o63 i 5 v cc i/o3 i/o4 i/o5 i/o6 i/o1 i/o2 i/o61 i/o57 i/o58 i/o59 i/o60 i/o56 i/o7 h0 h1 h2 h3 h4 h5 h6 h7 a7 a6 a5 a4 a3 a2 a1 a0 gnd gnd v cc i 2 i/o34 i/o33 i/o32 v cc i/o29 i/o28 i/o27 i/o26 i/o31 i/o30 i/o35 i/o39 i/o38 i/o37 i/o36 gnd i/o25 i/o24 e0 e1 e2 e3 e4 e5 e6 e7 d7 d6 d5 d4 d3 d2 d1 d0 17466g-030 i/o cell (0-7) p al block (a-h) c7
mach 4 family 41 100-pin pqfp connection diagram (m4(lv)-128/64) t op view 100-pin pqfp note: the numbers in parentheses re?ct compatible pin numbers for 84-pin plcc. pin designations i/clk = input or clock gnd = ground i= input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out trst = test reset enable = program i/o7 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 v cc gnd gnd v cc i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 h0 h1 h2 h3 h4 h5 h6 h7 gnd gnd tdi i5 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 io/clk0 gnd gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 b7 b6 b5 b4 b3 b2 b1 b0 c0 c1 c2 c3 c4 c5 c6 c7 tms tck gnd gnd 28 29 30 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 1 2 3 99 98 100 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 97 96 95 94 93 92 91 90 89 88 87 86 85 84 82 81 83 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 i/o40 i2 enable gnd gnd gnd td0 trst i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 g7 g6 g5 g4 g3 g2 g1 g0 i4/clk3 gnd gnd i3/clk2 i/o47 f1 f2 f3 f4 f5 f6 f7 f0 gnd 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 80 79 78 i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 gnd gnd i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 e0 e1 e2 e3 e4 e5 e6 e7 (83) (12) (13) (14) (15) (16) (17) (18) (19) (20) (23) (24) (25) (26) (27) (28) (29) (30) (31) (33) (34) (35) (36) (37) (38) (39) (40) (45) (46) (47) (48) (49) (50) (51) (52) (62) (61) (60) (59) (58) (57) (56) (55) (54) (41) (73) (72) (71) (70) (69) (68) (67) (66) (65) (10) (9) (8) (7) (6) (5) (4) (3) (82) (81) (80) (79) (78) (77) (76) (75) v cc v cc v cc v cc v cc v cc 17466g-031 i/o cell (0-7) p al block (a-h) c7
42 mach 4 family 100-pin tqfp connection diagram (m4(lv)-128/64) t op view 100-pin tqfp pin designations clk/i = clock or input gnd = ground i= input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out trst = test reset enable = program 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 gnd tdi i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 i0/clk0 v cc gnd i1/clk1 i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 tms tck gnd b7 b6 b5 b4 b3 b2 b1 b0 c0 c1 c2 c3 c4 c5 c6 c7 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 gnd gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i2 v cc gnd gnd v cc i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd gnd d7 d6 d5 d4 d3 d2 d1 d0 e0 e1 e2 e3 e4 e5 e6 e7 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 gnd gnd i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 v cc gnd gnd v cc i5 i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 gnd gnd a7 a6 a5 a4 a3 a2 a1 a0 h0 h1 h2 h3 h4 h5 h6 h7 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 gnd tdo trst i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 i4/clk3 gnd v cc i3/clk2 i/o47 i/o46 i/o45 i/o44 i/o43 i/o42 i/o41 i/o40 enable gnd g7 g6 g5 g4 g3 g2 g1 g0 f0 f1 f2 f3 f4 f5 f6 f7 17466g-032 i/o cell (0-7) p al block (a-h) c7
mach 4 family 43 144-pin tqfp connection diagram (m4(lv)-192/96) t op view 144-pin tqfp pin designations clk = clock gnd = ground i= input i/o = input/output v cc = supply voltage tdi = test data in tck = test clock tms = test mode select tdo = test data out 17466g-033 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 gnd tdi i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 i2 i3 v cc gnd i4 i/o8 i/o9 i/o10 i/o11 i/o12 i/o13 i/o14 i/o15 gnd v cc i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 tms tck gnd d7 d6 d5 d4 d3 d2 d1 d0 c7 c6 c5 c4 c3 c2 c1 c0 e7 e6 e5 e4 e3 e2 e1 e0 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i5 i6 i7 clk1 gnd v cc clk2 i8 i9 i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 v cc gnd i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 f7 f6 f5 f4 f3 f2 f1 f0 g0 g1 g2 g3 g4 g5 g6 g7 h0 h1 h2 h3 h4 h5 h6 h7 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd v cc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 i1 i0 clk0 gnd v cc clk3 i15 i14 i13 i/o79 i/o78 i/o77 i/o76 i/o75 i/o74 i/o73 i/o72 gnd b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 l0 l1 l2 l3 l4 l5 l6 l7 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 gnd tdo nc i/o71 i/o70 i/o69 i/o68 i/o67 i/o66 i/o65 i/o64 i12 v cc gnd i11 i10 i/o63 i/o62 i/o61 i/o60 i/o59 i/o58 i/o57 i/o56 gnd v cc i/o55 i/o54 i/o53 i/o52 i/o51 i/o50 i/o49 i/o48 nc gnd k0 k1 k2 k3 k4 k5 k6 k7 j0 j1 j2 j3 j4 j5 j6 j7 i0 i1 i2 i3 i4 i5 i6 i7 i/o cell (0-7) p al block (a-l) c7 17466g-044
44 mach 4 family 208-pin pqfp connection diagram (m4(lv)-256/128) t op view 208-pin pqfp c7 c6 c5 c4 c3 c2 c1 c0 d7 d6 d5 d4 d3 d2 d1 d0 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f2 f3 f4 f5 f6 f7 gnd tdi i/o16 i/o17 i/o18 i/o19 i/o20 i/o21 i/o22 i/o23 vcc gnd i/o24 i/o25 i/o26 i/o27 i/o28 i/o29 i/o30 i/o31 i2 i3 gnd vcc vcc gnd gnd vcc vcc gnd i4 i/o32 i/o33 i/o34 i/o35 i/o36 i/o37 i/o38 i/o39 gnd vcc i/o40 i/o41 i/o42 i/o43 i/o44 i/o45 i/o46 i/o47 tms tck gnd gnd i/o48 i/o49 i/o50 i/o51 i/o52 i/o53 i/o54 i/o55 gnd vcc i/o56 i/o57 i/o58 i/o59 i/o60 i/o61 i/o62 i/o63 i5 i6 clk1 vcc gnd gnd vcc vcc gnd gnd vcc clk2 i7 i8 i/o64 i/o66 i/o66 i/o67 i/o68 i/o69 i/o70 i/o71 vcc gnd i/o72 i/o73 i/o74 i/o75 i/o76 i/o77 i/o78 i/o79 gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 g7 g6 g5 g4 g3 g2 g1 g0 h7 h6 h5 h4 h3 h2 h1 h0 i0 i1 i2 i3 i4 i5 i6 i7 j0 j1 j2 j3 j4 j5 j6 j7 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 n7 n6 n5 n4 n3 n2 n1 n0 m7 m6 m5 m4 m3 m2 m1 m0 l0 l1 l2 l3 l4 l5 l6 l7 k0 k1 k2 k3 k4 k5 k6 k7 b7 b6 b5 b4 b3 b2 b1 b0 a7 a6 a5 a4 a3 a2 a1 a0 p0 p1 p2 p3 p4 p5 p6 p7 o0 o1 o2 o3 o4 o5 o6 o7 gnd i/o15 i/o14 i/o13 i/o12 i/o11 i/o10 i/o9 i/o8 gnd vcc i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 i1 i0 clk0 vcc gnd gnd vcc vcc gnd gnd vcc clk3 i13 i12 i/o127 i/o126 i/o125 i/o124 i/o123 i/o122 i/o121 i/o120 vcc gnd i/o119 i/o118 i/o117 i/o116 i/o115 i/o114 i/o113 i/o112 gnd gnd tdo trst i/o111 i/o110 i/o109 i/o108 i/o107 i/o106 i/o105 i/o104 vcc gnd i/o103 i/o102 i/o101 i/o100 i/o99 i/o98 i/o97 i/o96 i11 gnd vcc vcc gnd gnd vcc vcc gnd i10 i9 i/o95 i/o94 i/o93 i/o92 i/o91 i/o90 i/o89 i/o88 gnd vcc i/o87 i/o86 i/o85 i/o84 i/o83 i/o82 i/o81 i/o80 enable gnd 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 recommend to tie to vcc recommend to tie to gnd pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell (0-7) p al block (a-hx) clock ground input input/output no connect supply voltage t est data in t est clock t est mode select t est data out t est reset program c7 17466g-044 17466h-066
mach 4 family 45 256-ball bga connection diagram (m4lv-256/128) bottom view 256-ball bga gnd gnd i/o116 o3 i/o120 p7 i/o123 p4 gnd i12 gnd n/c gnd n/c n/c gnd i1 a b c d e f g h j k l m n p r t u v w y a b c d e f g h j k l m n p r t u v w y n/c i/o113 o6 n/c i/o117 o2 i/o119 o0 i/o122 p5 i/o125 p2 i/o127 p0 n/c clk3 clk0 n/c i/o0 a0 i/o1 a1 gnd n/c vcc i/o112 o7 i/o114 o5 i/o118 o1 i/o121 p6 i/o126 p1 n/c n/c n/c n/c i/o2 a2 i/o6 a6 i/o108 n4 i/o109 n5 trst vcc tdi i/o115 o4 vcc i/o124 p3 i13 n/c n/c i0 i/o3 a3 vcc i/o105 n1 i/o106 n2 i/o111 n7 vcc gnd i/o103 m7 i/o107 n3 i/o110 n6 i/o100 m4 i/o102 m6 i/o104 n0 vcc i/o96 m0 i/o98 m2 i/o101 m5 n/c gnd n/c i/o97 m1 i/o99 m3 gnd i11 n/c n/c gnd n/c i10 i9 gnd n/c i/o94 l1 i/o92 l3 gnd i/o82 k5 vcc i/o79 j7 i/o77 j5 i/o73 j1 i/o70 i6 i/o66 i2 n/c n/c n/c n/c i/o61 h2 i/o57 h6 gnd 20 19 18 17 16 15 14 13 12 11 10 9 i/o95 l0 i/o93 l2 i/o90 l5 n/c 8 i/o91 l4 i/o89 l6 i/o86 k1 vcc 7 gnd i/o88 l7 i/o84 k3 i/o81 k6 6 i/o87 k0 i/o85 k2 i/o80 k7 vcc 5 n/c i/o83 k6 enable vcc tdo i/o76 j4 vcc i/o67 i3 i7 n/c n/c i6 i/o60 h3 vcc 43 gnd n/c i/o78 j6 i/o75 j3 i/o72 j0 i/o69 i5 i/o65 i1 i/o64 i0 n/c clk2 clk1 i/o63 h0 i/o59 h4 i/o58 h5 21 20 19 18 17 16 15 14 13 12 11 10 987654321 gnd i/o74 j2 i/o71 i7 i/o68 i4 gnd i8 gnd n/c n/c gnd i/o62 h1 gnd i5 gnd i/o4 a4 i/o7 a7 i/o5 a5 i/o8 b0 i/o11 b3 i/o9 b1 i/o12 b4 i/o15 b7 n/c tck vcc vcc i/o18 c5 vcc i/o24 d7 i/o29 d2 i2 n/c i/o35 e3 i/o54 g1 i/o50 g5 i/o48 g7 n/c vcc n/c vcc i/o51 g4 tms vcc i/o56 h7 i/o55 g0 i/o53 g2 gnd n/c n/c i/o10 b2 gnd gnd i/o13 b5 i/o14 b6 gnd vcc n/c gnd i/o16 c7 n/c n/c i/o17 c6 i/o19 c4 i/o20 c3 i/o21 c2 i/o22 c1 gnd i/o23 c0 i/o25 d6 i/o26 d5 i/o27 d4 i/o28 d3 i/o30 d1 i/o31 d0 n/c gnd i3 n/c gnd n/c i4 gnd i/o33 e1 n/c gnd vcc n/c gnd i/o37 e5 i/o34 e2 i/o32 e0 i/o41 f1 i/o38 e6 i/o36 e4 i/o43 f3 i/o39 e7 gnd i/o46 f6 i/o42 f2 i/o40 f0 i/o47 f7 i/o45 f5 i/o44 f4 i/o52 g3 i/o49 g6 n/c n/c gnd gnd pin designations clk gnd i i/o n/c vcc tdi tck tms tdo trst enable = = = = = = = = = = = = i/o cell (0-7) p al block (a-p) clock ground input input/output no connect supply voltage t est data in t est clock t est mode select t est data out t est reset program c7 17466g-045
46 mach 4 family mach 4 product ordering information mach 4 devices commercial & industrial - 3.3v and 5v lattice/vantis programmable logic products are available with several ordering options. the order number (valid com- bination) is formed by a combination of: all mach devices are dual-marked with both commercial and industrial grades. the industrial speed grade is slower, i.e., m4-256/128-7yc-10yi v alid combinations v alid combinations list con?urations planned to be supported in volume for this device. consult the local lattice sales of?e to con?m availability of speci? valid combinations and to check on newly released combinations. 128 f amily type m4- = mach 4 family (5-v v cc ) m4lv- = mach 4 family low voltage (3.3-v v cc ) m4- 256 y c macrocell density 32 = 32 macrocells 128n = 128 macrocells, non-isp 64 = 64 macrocells 192 = 192 macrocells 96 = 96 macrocells 256 = 256 macrocells 128 = 128 macrocells i/os /32 = 32 i/os in 44-pin plcc, 44-pin tqfp or 48-pin tqfp /48 = 48 i/os in 100-pin tqfp /64 = 64 i/os in 84-pin plcc, 100-pin pqfp or 100-pin tqfp /96 = 96 i/os in 144-pin tqfp /128 = 128 i/os in 208-pin pqfp or 256-ball bga operating conditions c= commercial (0 c to +70 c) i= industrial (-40 c to +85 c) p ackage type a= ball grid array (bga) j= plastic leaded chip carrier (plcc) v= thin quad flat pack (tqfp) y= plastic quad flat pack (pqfp) speed -7 = 7.5 ns t pd -10 = 10 ns t pd -12 = 12 ns t pd -14 = 14 ns t pd -15 = 15 ns t pd -18 = 18 ns t pd -7 48 = 48-pin tqfp for m4(lv)-32/32 or m4(lv)-64/32 / v alid combinations m4-32/32 -7, -10, -12, -15 jc, vc, vc48 m4lv-32/32 jc, vc, vc48 m4-64/32 jc, vc, vc48 m4lv-64/32 jc, vc, vc48 m4-96/48 vc m4lv-96/48 vc m4-128/64 yc, vc m4lv-128/64 yc, vc m4-128n/64 jc m4lv-128n/64 jc m4-192/96 vc m4lv-192/96 vc m4-256/128 yc m4lv-256/128 yc, ac v alid combinations m4-32/32 -10, -12, -14, -18 ji, vi, vi48 m4lv-32/32 ji, vi, vi48 m4-64/32 ji, vi, vi48 m4lv-64/32 ji, vi, vi48 m4-96/48 vi m4lv-96/48 vi m4-128/64 yi, vi m4lv-128/64 yi, vi m4-128n/64 ji m4lv-128n/64 ji m4-192/96 vi m4lv-192/96 vi m4-256/128 yi m4lv-256/128 yi, ai

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